Capacitor Structures

ABSTRACT

Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereover. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.

TECHNICAL FIELD

1. This invention relates to integrated circuitry capacitors and methodsof forming the same.

BACKGROUND OF THE INVENTION

2. One common goal in capacitor fabrication is to maximize thecapacitance for a given size capacitor. It is desirable that storedcharge be at a maximum immediately at the physical interface between therespective electrodes or capacitor plates and the capacitor dielectricmaterial between the plates. Typical integrated circuitry capacitorshave electrodes or plates which are formed from doped semiconductivematerial such as polysilicon. The polysilicon is usually heavily dopedto impart a desired degree of conductivity for satisfactory capacitorplate operation.

3. One drawback of heavily doping polysilicon is that during operation acharge depletion region develops at the interface where chargemaximization is desired. Hence, a desired level of charge storage isachieved at a location which is displaced from the interface between thecapacitor plate and the dielectric material.

4. Another drawback of heavily doping the polysilicon capacitor platesis that during processing, some of the dopant can migrate away from thepolysilicon and into other substrate structures. Dopant migration canadversely affect the performance of such structures. For example, onetype of integrated circuitry which utilizes capacitors are memory cells,and more particularly dynamic random access memory (DRAM) devices.Migratory dopants from doped polysilicon capacitor plates can adverselyimpact adjacent access transistors as by undesirably adjusting thethreshold voltages.

5. As the memory cell density of DRAMs increases there is a continuouschallenge to maintain sufficiently high storage capacitance despitedecreasing cell area. Additionally there is a continuing goal to furtherdecrease cell area. The principal way of increasing cell capacitanceheretofore has been through cell structure techniques. Such techniquesinclude three dimensional cell capacitors such as trench or stackedcapacitors.

6. This invention arose out of concerns associated with improvingintegrated circuitry capacitors. This invention also grew out ofconcerns associated with maintaining and improving the capacitance andcharge storage capabilities of capacitors utilized in memory cellscomprising DRAM devices.

SUMMARY OF THE INVENTION

7. Integrated circuitry capacitors and methods of forming the same aredescribed. In accordance with one implementation, a capacitor plate isformed and a conductive layer of material is formed thereover.Preferably, the conductive layer of material is more conductive than thematerial from which the capacitor plate is formed. In a preferredimplementation, the conductive layer of material comprises a titanium ortitanium-containing layer. Other materials can be used such as chemicalvapor deposited platinum, TiN, and the like. In another preferredimplementation, the capacitor plate comprises an inner capacitor platehaving an outer surface with a generally roughened surface area. In oneaspect of this implementation, the roughened surface area compriseshemispherical grain polysilicon. Capacitors formed in accordance withthe invention are particularly well suited for use in dynamic randomaccess memory (DRAM) circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

8. Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

9.FIG. 1 is a view of a semiconductor wafer fragment undergoingprocessing in accordance with the invention.

10.FIG. 2 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown in FIG. 1.

11.FIG. 3 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown in FIG. 2.

12.FIG. 4 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown in FIG. 3.

13.FIG. 5 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown in FIG. 4.

14.FIG. 6 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown in FIG. 5.

15.FIG. 7 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown in FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

16. This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

17. Referring to FIG. 1, a semiconductor wafer fragment in process isindicated generally at 10 and includes a semiconductor substrate 12. Inthe context of this document, the term “semiconductor substrate” isdefined to mean any construction comprising semiconductor material,including, but not limited to, bulk semiconductor materials such as asemiconductor wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductor material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductor substrates described above.

18. Isolation oxide regions 14 are formed relative to substrate 12 anddefine therebetween a substrate active area over which a plurality ofcapacitors are to be formed. Conductive lines 16, 18, 20, and 22 areprovided over substrate 12. Such lines typically include, as shown forline 16, a thin oxide layer 24, a conductive polysilicon layer 26, asilicide layer 28, a protective insulative cap 30, and sidewall spacers32. A plurality of diffusion regions 17, 19, and 21 are received withinsubstrate 12 and constitute source/drain regions for transistors whichserve as access transistors for the capacitors to be formed. Diffusionregions 17, 19 and 21 define substrate node locations with whichelectrical communication is desired. An insulative layer 34 is formedover substrate 12 and typically comprises an oxides such asborophosphosilicate glass. Of course, other materials such asphosphosilicate glass, borosilicate glass, and the like can be used.Subsequently, insulative layer 34 is patterned and etched to defineopenings 36, 38 over diffusion regions 17, 21 respectively, and relativeto which capacitors are to be formed. Insulative layer 34 defines asubstrate outer surface 35.

19. A first layer 40 is formed over substrate outer surface 35. Anexemplary and preferred material for layer 40 comprises a conductive orsemiconductive material such as conductively doped polysilicon. Layer 40defines at least a portion of a first or inner capacitor plate. Layer 40also has a first conductivity and defines a capacitor plate which isoperably adjacent and in electrical communication with the nodelocations defined by diffusion regions 17 and 21. Accordingly, layer 40is electrically connected with the node locations defined by diffusionregions 17, 21.

20. Referring to FIG. 2, a second layer 42 is formed over first layer40. In a preferred implementation, second layer 42 comprises aconductive material which constitutes roughened or rugged polysilicon.An exemplary and preferred roughened or rugged polysilicon ishemispherical grain polysilicon. Such is, in one aspect, substantiallyundoped as formed over first layer 40. Subsequently, and throughsuitable processing, outdiffusion of dopant from conductively dopedpolysilicon layer 40 into layer 42 renders second layer 42 conductive.Together, layers 40 and 42 constitute a doped semiconductive materialhaving a first average conductivity. Accordingly, layers 40 and 42constitute a first or inner capacitor plate having an outermost surface44 of hemispherical grain polysilicon. Accordingly, outermost surface 44defines a generally roughened surface area.

21. Referring to FIG. 3, a layer 46 is formed over substrate 12 andouter surface 44 of layer 42. According to one aspect, layer 46constitutes a conductive material having a second average conductivitywhich is greater than the first average conductivity of layers 40, 42. Apreferred manner of forming layer 46 is through suitable chemical vapordeposition thereof over layer 42. Accordingly, such forms a generallyconformal layer over the roughened surface area of the preferredhemispherical grain polysilicon layer 42. Hence, layer 46 is disposedover and operably adjacent layers 40, 42.

22. Suitable materials for layer 46 include conductive metal compounds,metal alloys, and elemental metals. Other suitable materials includethose which are preferably not conductively doped semiconductivematerial such as polysilicon. Accordingly, layer 46 constitutes amaterial other than doped semiconductive material. An exemplary andpreferred material for layer 46 is elemental titanium which is chemicalvapor deposited over layer 42. Other materials can be used such aschemical vapor deposited platinum, TiN, and the like. Layer 46 ispreferably chemical vapor deposited directly onto the hemisphericalgrain polysilicon material of layer 42.

23. Referring to FIG. 4, layers 40, 42, and 46 are planarized toelectrically isolate the layers within respective opening 36, 38.Exemplary planarization techniques include mechanical abrasion of thesubstrate as by chemical mechanical polishing. Other techniques arepossible.

24. Referring to FIG. 5, a capacitor dielectric layer 48 is formedoperably proximate the first capacitor plate, over layer 46 and withinopenings 36, 38. Accordingly, layer 48 is spaced from the material oflayers 40, 42 a distance which is defined by layer 46. Exemplarymaterials for layer 48 are Si₃N₄ and SiO₂ alone, or in combination.Other materials such as tantalum pentoxide (Ta₂O₅), barium strontiumtitanate (BST), and other dielectric materials can be used.

25. Alternately considered, the preferred metal layer 46 is formedintermediate conductive capacitor plate 40, 42 and capacitor dielectriclayer 48 preferably by chemical vapor deposition prior to providingcapacitor dielectric layer 48. As formed, metal layer 46 is at least inpartial physical contacting relationship with capacitor dielectric layer48. Accordingly, layer 46 is interposed between capacitor plate 40, 42and dielectric layer 48. In a most preferred aspect, conductive layer 46consists essentially of non-semiconductive material such as titanium, ortitanium silicide.

26. Referring to FIG. 6, a second capacitor plate layer 50 is formedover dielectric layer 48 and operatively proximate layer 46. In apreferred implementation, layer 50 defines an outer capacitor platewhich defines a cell plate layer of a DRAM storage capacitor. Anexemplary material for capacitor plate layer 50 is polysilicon.

27. Referring to FIG. 7, individual storage capacitors are patterned andetched to form capacitors 52, 54. An insulative layer 56 is formedthereover and is subsequently patterned and etched to form an openingwhich outwardly exposes diffusion region 19. Subsequently formedconductive material 58 provides a conductive bit line contact plug, anda subsequently formed conductive layer 60 provides a bit line inoperative electrical contact therewith. Accordingly, such defines, inthe illustrated and preferred embodiment, DRAM storage cells comprisingstorage capacitors 52, 54. The FIG. 7 construction illustrates but oneexample of DRAM storage cell constructions. Of course, otherconstructions which utilize the inventive methodology are possible

28. The above-described methodology and capacitor constructions providea desirable solution to concerns associated with charge depletioneffects at the interface between a capacitor plate and a dielectriclayer. The interpositioning of a layer of conductive material relativeto the capacitor plate and the dielectric layer, which is moreconductive than capacitor plate, effectively relocates the location ofthe capacitor's stored charge to a more desirable location. In addition,in implementations where doped semiconductive material is utilized foran inner capacitor plate and the “more conductive” interposed layer isformed thereover, a lesser degree of doping can be utilized such thatdopant migration into other substrate structures is reduced. This isparticularly useful when the capacitor plate includes an additionallayer which is generally undoped as formed and subsequently renderedsuitably conductive by outdiffusion of dopant from an adjacent layer.

29. In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming a capacitor comprising: forming a conductivecapacitor plate; forming a capacitor dielectric layer operably proximatethe capacitor plate; and forming a metal layer intermediate theconductive capacitor plate and the capacitor dielectric layer.
 2. Themethod of claim 1 , wherein the forming of the metal layer compriseschemical vapor depositing an elemental metal layer over the conductivecapacitor plate prior to providing the capacitor dielectric layer. 3.The method of claim 1 , wherein the forming of the metal layer compriseschemical vapor depositing a titanium layer over the conductive capacitorplate.
 4. The method of claim 1 , wherein the forming of the metal layercomprises chemical vapor depositing a titanium silicide layer over theconductive capacitor plate.
 5. The method of claim 1 , wherein theforming of the metal layer comprises chemical vapor depositing aplatinum layer over the conductive capacitor plate.
 6. The method ofclaim 1 , wherein the forming of the metal layer comprises chemicalvapor depositing a TiN layer over the conductive capacitor plate.
 7. Themethod of claim 1 , wherein the conductive capacitor plate comprisespolysilicon and the forming of the metal layer comprises chemical vapordepositing the metal layer onto the polysilicon.
 8. The method of claim1 , wherein the conductive capacitor plate comprises hemispherical grainpolysilicon and the forming of the metal layer comprises chemical vapordepositing a titanium layer onto the hemispherical grain polysilicon. 9.A method of forming a capacitor comprising: forming a conductivecapacitor plate comprising polysilicon; forming a capacitor dielectriclayer operably proximate the conductive capacitor plate; and forming ametal layer intermediate the conductive capacitor plate and thecapacitor dielectric layer.
 10. The method of claim 9 , wherein themetal layer is formed to be at least in partial physical contactingrelationship with the capacitor dielectric layer.
 11. The method ofclaim 9 , wherein the forming of the metal layer comprises chemicalvapor depositing the metal layer over the conductive capacitor plate.12. The method of claim 9 further comprising: prior to the forming ofthe metal layer, forming a doped polysilicon layer over a substrate anda layer comprising roughened polysilicon over the doped polysiliconlayer to form the conductive capacitor plate; and wherein the forming ofthe metal layer comprises chemical vapor depositing the metal layer overthe roughened polysilicon layer.
 13. The method of claim 9 furthercomprising: prior to the forming of the metal layer, forming a dopedpolysilicon layer over a substrate and a layer comprising undopedhemispherical grain polysilicon over the doped polysilicon layer to formthe conductive capacitor plate; outdiffusing dopant from the dopedpolysilicon layer into the hemispherical grain polysilicon layer; andwherein the forming of the metal layer comprises chemical vapordepositing a titanium layer over the hemispherical grain polysiliconlayer.
 14. A method of forming a capacitor comprising: forming acapacitor plate layer comprising conductively doped roughenedpolysilicon; forming a dielectric material layer operably proximate thecapacitor plate layer; and interposing a conductive layer between thecapacitor plate layer and the dielectric material layer, the conductivelayer being more conductive than the capacitor plate layer.
 15. Themethod of claim 14 , wherein the conductive layer consists essentiallyof non-semiconductive material.
 16. The method of claim 14 , wherein theconductive layer comprises titanium.
 17. The method of claim 14 ,wherein the roughened polysilicon comprises hemispherical grainpolysilicon and the interposing of the conductive layer compriseschemical vapor depositing a titanium-containing layer over thehemispherical grain polysilicon.
 18. A method of forming a capacitorcomprising: forming a conductive capacitor plate comprising roughenedpolysilicon; forming a capacitor dielectric layer operably proximate theconductive capacitor plate; and forming a metal layer consistingessentially of titanium intermediate the conductive capacitor plate andthe capacitor dielectric layer.
 19. The method of claim 18 , wherein theforming of the metal layer comprises chemical vapor depositing the layerover the capacitor plate.
 20. The method of claim 18 , wherein theroughened polysilicon layer comprises hemispherical grain polysiliconand the forming of the metal layer comprises chemical vapor depositingthe layer over the layer comprising hemispherical grain polysilicon. 21.A method of forming a capacitor comprising: forming a first layercomprising conductive material over a substrate outer surface; forming asecond layer comprising conductive material over the first layer ofconductive material; forming a layer comprising conductive metal overthe second layer; and forming a layer of dielectric material: and a cellplate layer operatively proximate the conductive metal layer to form acapacitor.
 22. The method of claim 21 , wherein: the forming of thefirst layer comprises forming conductively doped polysilicon over thesubstrate outer surface; and the forming of the second layer comprisesforming a layer comprising roughened polysilicon over the first layerand outdiffusing dopant from the first layer into the second layer. 23.The method of claim 21 , wherein: the forming of the first layercomprises forming conductively doped polysilicon over the substrateouter surface; and the forming of the second layer comprises forming alayer comprising hemispherical grain polysilicon over the first layerand outdiffusing dopant from the first layer into the second layer. 24.The method of claim 21 , wherein the forming of the layer comprising theconductive metal comprises chemical vapor depositing the metal over thesecond layer.
 25. The method of claim 21 , wherein: the forming of thesecond layer comprises forming a layer comprising hemispherical grainpolysilicon over the first layer; and the forming of the layercomprising the conductive metal comprises chemical vapor depositingelemental titanium over the layer comprising hemispherical grainpolysilicon.
 26. A method of forming a capacitor comprising: forming adoped semiconductive material over a substrate, the material having afirst average conductivity; forming a conductive material over the dopedsemiconductive material, the conductive material having a second averageconductivity which is greater than the first average conductivity;forming a capacitor dielectric layer over the conductive material; andforming an outer capacitor plate over the capacitor dielectric layer.27. The method of claim 26 , wherein the conductive material is notconductively doped semiconductive material.
 28. The method of claim 26 ,wherein the forming of the conductive material comprises forming amaterial other than doped semiconductive material over the dopedsemiconductive material.
 29. The method of claim 26 , wherein theforming of the conductive material comprises forming a layer ofelemental metal over the doped semiconductive material.
 30. The methodof claim 26 , wherein the forming of the conductive material comprisesforming a metal alloy layer over the doped semiconductive material. 31.The method of claim 26 , wherein the forming of the conductive materialcomprises forming a metal compound layer over the doped semiconductivematerial.
 32. The method of claim 26 , wherein: the forming of the dopedsemiconductive material comprises forming a layer comprising dopedpolysilicon over the substrate and forming a layer of hemisphericalgrain polysilicon over the layer comprising doped polysilicon; and theforming of the conductive material comprises chemical vapor depositing alayer of titanium over the layer of hemispherical grain polysilicon. 33.A method of forming a capacitor comprising: forming a first capacitorplate comprising an outer surface of hemispherical grain polysilicon;forming an elemental titanium layer over the outer surface; forming acapacitor dielectric layer over the elemental titanium layer; forming asecond capacitor plate over the capacitor dielectric layer.
 34. Themethod of claim 33 , wherein the forming of the elemental titanium layercomprises chemical vapor depositing the layer over the hemisphericalgrain polysilicon.
 35. The method of claim 33 , wherein the forming ofthe first capacitor plate comprises: forming a layer of conductivelydoped polysilicon over a substrate; forming a layer of hemisphericalgrain polysilicon over the layer of conductively doped polysilicon; andoutdiffusing dopant from the conductively doped polysilicon into thehemispherical grain polysilicon.
 36. A method of forming a DRAM storagecapacitor comprising: forming a capacitor opening relative to insulativelayer formed over a substrate, the capacitor opening being disposedelevationally over a node location with which electrical connection isto be made; forming a first polysilicon material layer within thecapacitor opening and in electrical communication with the nodelocation, the first polysilicon material layer having a firstconductivity; forming a second polysilicon material layer over the firstpolysilicon material layer, the second polysilicon material layer havingan outermost surface with a generally roughened surface area; forming alayer comprising a metal material over the second polysilicon materiallayer's outermost surface, the metal material layer having a secondconductivity which is greater than the first conductivity; forming alayer comprising a dielectric material over the metal material layer;and forming a cell plate layer over the dielectric material layer toform a storage capacitor.
 37. The method of claim 36 , wherein theforming of the second polysilicon material layer comprises forming alayer of hemispherical grain polysilicon over the first polysiliconmaterial layer.
 38. The method of claim 36 , wherein the forming of thelayer comprising a metal material comprises chemical vapor depositing alayer comprising titanium over the second polysilicon material layer'soutermost surface.
 39. A capacitor comprising: a substrate having a nodelocation; an insulative layer disposed over the substrate and having anopening over the node location; a first polysilicon material layerhaving a first conductivity, the layer being disposed within the openingand operably connected with the node location; a second polysiliconmaterial layer over the first polysilicon material layer, the secondpolysilicon material layer having an outermost surface with a generallyroughened surface area; a non-polysilicon conductive layer over thesecond polysilicon material layer's outermost surface, the conductivelayer having a second conductivity which is greater than the firstconductivity; a capacitor dielectric layer over the conductive materiallayer; and a capacitor plate over the capacitor dielectric layer. 40.The capacitor of claim 39 , wherein the capacitor plate comprises a cellplate layer which constitutes a portion of DRAM circuitry.
 41. Thecapacitor of claim 39 , wherein the second polysilicon materialcomprises hemispherical grain polysilicon.
 42. The capacitor of claim 39, wherein the conductive material layer comprises elemental titanium ora titanium alloy.
 43. The capacitor of claim 39 , wherein the conductivematerial layer comprises TiN.
 44. The capacitor of claim 39 , whereinthe conductive material layer comprises platinum.
 45. A capacitorcomprising: a substrate having a node location; a doped semiconductivematerial capacitor plate operably proximate the node location; a metallayer disposed over and operably proximate the first capacitor plate; acapacitor dielectric layer disposed over the metal layer and spaced fromthe semiconductive material capacitor plate; and a capacitor plate overthe capacitor dielectric layer.
 46. A capacitor comprising: a substratehaving a node location; a conductive inner capacitor plate comprisingpolysilicon operably proximate the node location; a metal layer disposedover and in physical contact with the conductive capacitor plate; acapacitor dielectric layer disposed over the metal layer and in physicalcontact therewith; and an outer capacitor plate over the capacitordielectric layer.
 47. A capacitor comprising: a substrate having a nodelocation; an inner conductive capacitor plate having a doped roughenedpolysilicon outer surface, the plate being connected with the nodelocation and having a first average conductivity; a conductive layerconnected with the inner conductive capacitor plate and having a secondaverage conductivity which is greater than the first averageconductivity; a dielectric layer connected with the conductive layer;and an outer conductive capacitor plate connected with the dielectriclayer.
 48. A capacitor comprising: a substrate having a node location;an inner conductive capacitor plate having a roughened outer surfacecomprising hemispherical grain polysilicon; a metal layer consistingessentially of titanium conformally proximate the roughened outersurface and connected with the capacitor plate; a capacitor dielectriclayer over the metal layer; and an outer conductive capacitor plateconnected with the dielectric layer.
 49. A capacitor comprising: asubstrate having an outer surface; a first layer comprising conductivematerial over the outer surface; a second layer comprising conductivematerial over the first layer of material, the first and second layersbeing different from one another, the second layer having an outerroughened surface; a conductive titanium-containing layer disposed inconformal physical contacting relation with the second layer; adielectric layer over the titanium-containing layer; and a cell platelayer operatively proximate the dielectric layer.
 50. A capacitorcomprising: a substrate having an outer surface; a doped semiconductivematerial over the outer surface and having a first average conductivity;a conductive material over the doped semiconductive material, theconductive material having a second average conductivity which isgreater than the first average conductivity, the doped semiconductivematerial and the conductive material comprising an inner capacitorplate; a capacitor dielectric layer over the conductive material; and anouter capacitor plate over the capacitor dielectric layer.
 51. Acapacitor comprising: a first capacitor plate comprising an outersurface of hemispherical grain polysilicon; an elemental titanium layerover the outer surface; a capacitor dielectric layer over the elementaltitanium layer; and a second capacitor plate over the capacitordielectric layer.